Semiconductor integrated circuits are universally used in microelectronic devices because of their seemingly endless potential for differing applications coupled with their miniature size. Examples of widely used types of integrated circuits are bipolar transistors, complementary metal oxide semiconductors (CMOS), double diffused metal oxide semiconductors (DMOS) and bipolar complementary metal oxide semiconductors (BICMOS), as well as many other types of devices. It is not unusual for there to be thousands of individual integrated circuits provided on a single substrate for a particular application.
However, in order to ensure proper functioning of the individual integrated circuits and the entire package as a whole, the various semiconductor integrated circuits must be electrically isolated from each other. The electrical isolation is necessary so as to prevent formation of parasitic device-to-device electrical currents and/or parasitic device-to-substrate electrical currents between the integrated circuits. These parasitic currents are detrimental in that they degrade the electrical charge-transporting capabilities of the affected integrated circuit.
In order to achieve this device isolation, it is common practice to surround the individual integrated circuits with a dielectric material, such as silicon oxide, which prevents conduction of electrical current through the material. Generally, a silicon oxide sidewall is formed around each of the integrated circuits. The silicon oxide, which is electrically non- conductive, surrounds the doped, electrically conductive, epitaxial silicon region containing the charge-carrying components of the device. The silicon oxide sidewalls prevent electrical current from passing between the isolated integrated circuits. However, there are several shortcomings associated with the use of this method of dielectric isolation. Because the epitaxial silicon regions are generally heavily doped and therefore electrically conductive, an electrically conductive channel is formed along the undoped oxide sidewalls when electrical charges are passed within the epitaxial region. This electrically conductive channel is parasitic in that it depletes the integrated circuit of usable electrical current and thereby diminishes its full charge carrying ability. Because of the formation of this parasitic channel, the efficiency of the integrated circuit is lowered and the maximum voltage which can be used is detrimentally limited.
Therefore it would be desirable to provide a method for dielectrically isolating individual semiconductor integrated circuits, which does not result in the formation of parasitic charge-depleting effects that consequently hamper the operability of the integrated circuit.
In addition, it would also be desirable if this method for dielectrically isolating the integrated circuits simultaneously resolved another shortcoming associated with the formation of these types of integrated circuits. Generally, the semiconductor integrated circuit contains an electrically conductive buried layer within the epitaxial silicon. Accordingly a low resistivity electrical contact is required to make contact to this buried layer. In order to form this electrical contact, a long diffusion period is typically required to traverse the entire thickness of epitaxial silicon (to the buried layer) with the dopant material, so as to ensure that the entire contact is appropriately doped to be of a higher electrical conductivity.
However, as dopant diffusion is occurring vertically through the material for formation of the contact to the buried layer, diffusion is also occurring laterally. Therefore, during a long diffusion period, such as that required for formation of the contact to the buried layer, there is a significant amount of unwanted lateral diffusion also. In practice, the thicker the epitaxial silicon layer which must be traversed by the contact in order to reach the buried layer, the wider the diffusion zone surrounding the contact to the buried layer will be. This results in diffusion zones around the electrical contacts of undesirably large widths, which accordingly consume excessively large amounts of area within the semiconductor material. This is particularly problematic, since the trend in microelectronics design is to constantly reduce the size of all of the integrated circuit components while concurrently enhancing their potential.
It would therefore be desirable to provide a method for forming these contacts to the buried layer within an integrated circuit which does not result in unnecessary lateral diffusion of the dopant material and which correspondingly permits narrower contacts. Further, it would be most desirable if such a method for forming these contacts were integral with the process for providing dielectric isolation between individual semiconductor devices, wherein the process for forming dielectric isolation avoids the shortcomings of the prior art, particularly the formation of parasitic charge-depleting effects.